1. Field of the Invention
The present invention generally relates to a method for forming a dual oxide layer, and more particularly to a method for forming a dual oxide layer having varying thicknesses by using a damage layer formed on the silicon substrate by dry etching, or a silicon nitride layer deposited on the silicon substrate.
2. Background of the Related Art
In the semiconductor industry, silicon dioxide (SiO.sub.2) is used in a variety of applications. Often, it is used as a dielectric or an insulative layer to electrically separate various regions or structures. Examples of use as a dielectric or an insulative layer include as a gate oxide on a MOS (Metal Oxide Semiconductor) device, as a dielectric of a capacitor, as an interlevel dielectric between metals, and for a field isolation.
When used as a gate oxide on a MOS device, the SiO.sub.2 layer needs to have excellent electrical characteristics. Particularly, as the mounting density of the semiconductor chip on the substrate has been improved, the thickness of the oxide layer has decreased, and the need for a gate oxide having excellent electrical characteristics and a thickness of 100 .ANG. or less has arisen.
As the operational speed of electrical systems has increased, a merged IC, comprising a logic device, SRAM (Static Random Access Memory), DRAM (Dynamic RAM), and ROM (Read Only Memory) within one single chip, has been developed. Since each of the individual devices within the merged IC has a different operational speed and driving condition, each device requires a certain oxide layer thickness. This oxide layer, which has these varying thicknesses, is hereinafter referred to as a "dual oxide layer", and is particularly used where an oxide layer with excellent electrical characteristics is required. For example, a merged IC, comprising a memory device and a logic device such as a microprocessor within one single chip, requires a dual oxide layer having excellent uniformity and a thickness of 100 .ANG. or less. This requirement of a dual oxide layer also applies to microprocessors, such as the CPU of a computer system, having an operational speed of 700 MHZ or more.
In the dual oxide layer, a relatively thick part may be used as the gate oxide of a DRAM memory cell transistor. Since a voltage higher than a positive power supply voltage (V.sub.cc) (for example, V.sub.cc +2V.sub.th, wherein V.sub.th is a threshold voltage of the memory cell transistor) is provided to a gate electrode so as to drive word lines, the part having the greater thickness is used as the gate oxide of the DRAM.
The need for another oxide layer growth process to form the dual oxide layer is a very complicated procedure, resulting in reduced productivity of the procedure. Further, interaction among the oxide layer growth processes on one wafer makes it difficult to form the dual oxide layer having the designated thickness at a predetermined position. This interaction among the oxide layer growth processes is most severe during formation of an ultra thin dual oxide layer.
Accordingly, a need exists for a process to form the dual oxide layer using only one oxidation process.